EP2S15F672C4 vs EP2S15F672C5N Comparación
Comparación detallada lado a lado de EP2S15F672C4 por Altera y EP2S15F672C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S15F672C4 | EP2S15F672C5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $235,00 | $121,90 |
| Family | Stratix II | Stratix II |
| Logic Elements | 15,600 | 15,600 |
| Embedded Memory Bits | 419,328 bits | — |
| DSP Blocks | 156 (approximate, per Stratix II family) | — |
| Maximum User I/Os | 366 | — |
| Encapsulado | 672-ball FineLine BGA (FBGA) | 672-BBGA / FBGA-672 |
| Process Node | 90 nm | — |
| PLLs | 6 | — |
| Temperatura de funcionamiento | Commercial (0C to +85C, 'C' suffix) | 0C to +85C (commercial) |
| Speed Grade | 4 | -C5 |
| Configuration Method | Serial / Parallel (passive serial, fast passive parallel, JTAG) | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance per Altera product page] | RoHS Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| Nivel MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Series | — | Altera Stratix II |
| Logic Array Blocks (LABs) | — | 780 |
| Configurable Logic Blocks (CLBs) | — | 6,240 |
| Embedded Memory (bits) | — | 419,328 |
| User I/O Pins | — | 366 |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Maximum Internal Frequency | — | 640 MHz |
| Lead-Free (Pb-Free) | — | Yes |