EP2S30F672C4N vs EP2S30F672I4 Comparación
Comparación detallada lado a lado de EP2S30F672C4N por Altera y EP2S30F672I4 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S30F672C4N | EP2S30F672I4 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $121,00 | $695,00 |
| Series | Stratix II | Stratix II |
| Logic Elements | 33,880 | 33880 |
| Total RAM Bits | 1,369,728 | 1369728 |
| Number of LABs/CLBs | 1694 | — |
| Number of I/O | 500 | 500 |
| Encapsulado | 672-BBGA, FCBGA (FineLine BGA) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +85C (Commercial, C4 grade) | -40C to +100C (Industrial) |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Maximum Internal Frequency | 711.24 MHz | — |
| Speed Grade | C4 (Commercial, internal performance bin 4) | — |
| Nivel MSL | 3 (168 hours) | 3 (per JEDEC J-STD-020) |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free / halogen-free status] | — |
| Embedded Multipliers / DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceivers | N/A (Stratix II non-GX variant) | — |
| Configuration Method | Passive serial / Fast passive parallel / JTAG | — |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Array Blocks (LABs) | — | 1694 |
| DSP Blocks | — | 12 (per datasheet, family range) |
| Number of PLLs | — | 6 |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Encapsulado / Carcasa | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |