EP2S30F672I5 vs EP2S30F672I4 Comparación
Comparación detallada lado a lado de EP2S30F672I5 por Intel y EP2S30F672I4 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S30F672I5 | EP2S30F672I4 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $185,00 | $695,00 |
| Family | Stratix II | — |
| Logic Elements (LE) | 33,880 | — |
| Adaptive Logic Modules (ALM) | 13,567 (approx., per Stratix II family ratio) | — |
| Total RAM Bits | 1,368,576 (1.36 Mbit) | 1369728 |
| DSP Blocks | 16 (9-bit x 9-bit multipliers) | 12 (per datasheet, family range) |
| Maximum User I/Os | 500 (492 outputs reported) | — |
| Maximum Operating Frequency | 609.76 MHz | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Supply Voltage | 1.2 V | — |
| I/O Supply Voltage | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | — |
| Encapsulado | 672-ball FC-FBGA (FineLine BGA) | — |
| Ball Pitch | 1.00 mm | 1.0 mm |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Estado RoHS | Compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Lead-Free | Yes | — |
| Speed Grade | 5 (fast) | — |
| Series | — | Stratix II |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements | — | 33880 |
| Logic Array Blocks (LABs) | — | 1694 |
| Number of I/O | — | 500 |
| Number of PLLs | — | 6 |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Encapsulado / Carcasa | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |