EP2SGX60EF1152I3 vs EP2SGX60EF1152I4N Comparación

Comparación detallada lado a lado de EP2SGX60EF1152I3 por Intel y EP2SGX60EF1152I4N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Intel
EP2SGX60EF1152I4N EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N ✓ Activo

Comparación de especificaciones

Parámetro EP2SGX60EF1152I3 EP2SGX60EF1152I4N
Marca Intel Intel
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Obsolete Activo
Estado del stock In Stock In Stock
Precio unitario (USD) $365,00 $0,00
Family Stratix II GX —
Series EP2SGX60 —
Logic Elements (LEs) 60,440 —
Adaptive Logic Modules (ALMs) 30,220 (estimated from LEs) —
Equivalent Logic Cells (CLBs) 60,440 —
Embedded Memory (Bits) 2,544,192 bits (per DigiKey listing for the I4N variant) —
Maximum Internal Frequency 717 MHz —
Combinational Delay (per CLB) 2.99 ns —
Multi-Gigabit Transceivers [DATA_NEEDED: exact count for EP2SGX60] —
Maximum Transceiver Data Rate 6.375 Gbps (per Stratix II GX family spec) —
Total RAM Bits 2,544,192 bits —
Encapsulado 1152-ball FBGA, 35 mm x 35 mm, 1 mm pitch 1,152-ball FBGA
Pin/Ball Count 1152 —
Tipo de montaje Surface Mount (BGA) Surface mount
Temperatura de funcionamiento -40C to +100C (Industrial, I3 speed grade) —
Speed Grade I3 (Industrial) —
Configuration Mode Enhanced (EPC) - fast parallel via external memory —
Process Technology 90 nm CMOS —
Estado RoHS [DATA_NEEDED: not in retrieved snippets] —
Device Type — FPGA
Product Family — Stratix II GX
Logic Cells — 60,440
Embedded Memory — 2,544,192 bits
I/O Count — 534
Internal Frequency — 717 MHz
Tensión de alimentación — 1.2 V
Package Type — Other, 23 x 23 mm, 1 mm pitch, MS-034AAJ-1, FBGA-484
Pins — 484
Device Technology — 90 nm
Logic Blocks — 3,022 LABs
Operating Temperature Grade — Industrial
Compliance — [DATA_NEEDED: compliance certification details]
Transceiver Count — [DATA_NEEDED: high-speed transceiver count]
Configuration Memory — [DATA_NEEDED: configuration memory specification]
Package Pinout — [DATA_NEEDED: complete ball-map pinout]

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