EP2SGX90FF40C5NES vs EP2SGX90FF40C4NES Comparación
Comparación detallada lado a lado de EP2SGX90FF40C5NES por Altera y EP2SGX90FF40C4NES por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP2SGX90FF40C4NES - Stratix II GX FPGA, 90k LE, 6.375Gbps | Intel (Altera)
EP2SGX90FF40C4NES NrndComparación de especificaciones
| Parámetro | EP2SGX90FF40C5NES | EP2SGX90FF40C4NES |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.580,00 | $1.485,00 |
| Family | Stratix II GX | Stratix II GX |
| Series | EP2SGX90 | — |
| Logic Elements | 90,960 | 90,960 |
| Configurable Logic Blocks (CLBs) | 4,828 | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Maximum Core Frequency | 609.76 MHz | — |
| Encapsulado | 1508-pin FC-FBGA | 1508-pin FC-FBGA |
| Tipo de montaje | Surface Mount (flip-chip BGA) | Surface Mount (BGA) |
| Temperature Grade | Commercial Extended | — |
| Embedded Transceivers | Multi-gigabit transceiver (CMU) channels | — |
| On-chip Memory | M512/M4K/M-RAM blocks (TriMatrix memory) | — |
| DSP Blocks | Embedded multiplier/accumulator DSP blocks | Yes (dedicated multipliers/accumulator blocks) |
| PLL Count | Multiple PLLs with dedicated analog supply pins | — |
| Estado RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | C5 | — |
| Logic Array Blocks (LABs) | — | 4,828 |
| Maximum Transceiver Data Rate | — | 6.375 Gbps per channel |
| Number of Transceiver Channels | — | Up to 20 (device-dependent) |
| Embedded Memory | — | TriMatrix memory (M512/M4K/M-RAM blocks) |
| Operating Temperature Grade | — | Commercial Extended |
| Configuration Method | — | JTAG, Active Serial, Active Parallel |
| PLLs | — | Yes (multiple with deterministic latency) |