EP3SL200H780I4LN vs EP3SL200H780I4L Comparación
Comparación detallada lado a lado de EP3SL200H780I4LN por Altera y EP3SL200H780I4L por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP3SL200H780I4LN | EP3SL200H780I4L |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.280,00 | $1.395,00 |
| Series | Stratix III L | — |
| Family | Stratix III L (Low-Power) | Stratix III L |
| Manufacturer | Intel / Altera (now Intel PSG) | — |
| Number of Logic Elements / Cells | 200,000 | — |
| Number of LABs / CLBs | 8,000 | — |
| Total RAM Bits | 10,901,504 (approximately 10.9 Mbit) | — |
| Number of I/O | 488 | — |
| Voltage - Supply | 0.9 V core (selectable Vcore) | — |
| Temperatura de funcionamiento | -40C to +100C (industrial) | -40C to +100C (Industrial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Encapsulado / Carcasa | 780-BBGA, FCBGA (Flip-Chip BGA) | — |
| Process Technology | 65 nm CMOS | 65 nm CMOS |
| Speed Grade | I4 (Industrial, mid-speed grade) | I4 (Industrial) |
| Estado RoHS | RoHS Compliant (lead-free) | Compliant |
| Nivel MSL | MSL 3 (168 Hours, per JEDEC J-STD-020) | — |
| Roaming Pin Name Suffix | LN = lead-free, industrial temp, H780 780-ball package | — |
| Logic Elements | — | 200,000 |
| Logic Array Blocks (LABs) | — | 8,000 |
| Embedded Memory (Bits) | — | 10,901,504 |
| Maximum User I/O | — | 488 |
| Core Supply Voltage | — | 0.86 V to 1.15 V |
| Internal Performance | — | 375 MHz |
| Encapsulado | — | 780-pin FC-HFBGA (Flip-Chip) |
| Transceivers | — | Up to 24 channels |
| Transceiver Data Rate | — | Up to 6.375 Gbps |
| DSP Blocks | — | 9x9 / 18x18 / 36x36 multipliers |
| Memory Interface Support | — | DDR3, DDR2, DDR, QDR II+, RLDRAM II |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan |
| HardCopy Support | — | Compatible (Lattice-style migration path via HardCopy III) |