EP3SL340H1152I4 vs EP3SL340H1152C4N Comparación
Comparación detallada lado a lado de EP3SL340H1152I4 por Intel y EP3SL340H1152C4N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP3SL340H1152C4N - 340K LE Stratix III L FPGA, 1152-BGA | Intel
EP3SL340H1152C4N ⚠ Última compraComparación de especificaciones
| Parámetro | EP3SL340H1152I4 | EP3SL340H1152C4N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15.100,00 | $1.245,00 |
| Series | Stratix III L | — |
| Logic Elements (LE) | 337,500 | — |
| Embedded Memory | 18,821,440 bits | — |
| User I/O Pins | 744 | — |
| Logic Array Blocks (LABs) | 13,500 | 13,500 |
| Operating Frequency | 717 MHz (max fabric speed) | — |
| Process Technology | 65 nm CMOS | 65 nm CMOS |
| Core Voltage | 1.1 V | 1.1 V |
| Encapsulado | 1152-ball FCBGA / HBGA | 1152-ball FCBGA (FineLine BGA) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (I4: -40C to +100C junction) | — |
| I/O Standards Supported | LVDS, LVPECL, HSTL, SSTL, LVCMOS, LVTTL | — |
| Memory Interface Hard IP | DDR / DDR2 / DDR3 SDRAM controllers with PHY | — |
| Estado RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| Family | — | Stratix III L |
| Logic Elements | — | 337,500 |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory Bits | — | 18,821,144 |
| Embedded Multiplier Blocks | — | [DATA_NEEDED: 18x18 multiplier count] |
| User I/Os | — | 744 |
| Maximum Internal Frequency | — | 800 MHz (data); 500 MHz (logic) |
| Temperatura de funcionamiento | — | 0C to +85C (commercial) |
| Speed Grade | — | 4 |
| Configuration Methods | — | Passive Serial, Fast Passive Parallel, Active Serial |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |