EP610DC-35 vs EP610DC-15 Comparación
Comparación detallada lado a lado de EP610DC-35 por Altera y EP610DC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC-35 | EP610DC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,40 | $7,95 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns (speed grade -15) |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Encapsulado | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Tipo de montaje | Through-Hole (DIP) | Through-Hole |
| Temperatura de funcionamiento | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0C to 70C (commercial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Estado RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Programming Method | — | JEDEC fuse map, UV erasure |
| Technology | — | CMOS |