EP610ILC-10 vs EP610DC-30 Comparación
Comparación detallada lado a lado de EP610ILC-10 por Altera y EP610DC-30 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610ILC-10 | EP610DC-30 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,20 | $10,40 |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 | 16 (with output enable) |
| Dedicated Inputs | 4 | 16 |
| Tensión de alimentación | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Encapsulado | PLCC-28 (plastic J-lead chip carrier) | 24-pin CERDIP (windowed) |
| Tipo de montaje | Surface Mount (PLCC socket or solder) | Through-Hole |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | EP610 (Classic Device Family) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |