EP610ILC10 vs EP610IDC-10 Comparación
Comparación detallada lado a lado de EP610ILC10 por Intel y EP610IDC-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610ILC10 | EP610IDC-10 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,10 | $8,85 |
| Family | Classic EPLD (EP610) | — |
| Logic Elements | 16 macrocells | — |
| Gates | 300 gates equivalent | — |
| Product Terms | 160 | — |
| I/O Lines | 16 | — |
| Dedicated Inputs | 4 | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | — |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | — |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable (windowed ceramic) |
| Architecture | PAL-type AND-OR-NOT | — |
| Encapsulado | 28-pin PLCC (J-Lead) | — |
| Tipo de montaje | Surface Mount / Socket | Through-hole |
| Estado RoHS | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | — | 20 |
| Rango de temperatura de funcionamiento | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |