EP610ILC10 vs EP610ILC-25 Comparación
Comparación detallada lado a lado de EP610ILC10 por Intel y EP610ILC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610ILC10 | EP610ILC-25 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,10 | $9,85 |
| Family | Classic EPLD (EP610) | Classic EPLD (EP610 series) |
| Logic Elements | 16 macrocells | — |
| Gates | 300 gates equivalent | — |
| Product Terms | 160 | 160 |
| I/O Lines | 16 | — |
| Dedicated Inputs | 4 | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | — |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Architecture | PAL-type AND-OR-NOT | — |
| Encapsulado | 28-pin PLCC (J-Lead) | 28-pin PLCC (J-lead) |
| Tipo de montaje | Surface Mount / Socket | Surface Mount |
| Estado RoHS | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Macrocells | — | 16 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Rango de temperatura de funcionamiento | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |
| Programming Method | — | In-system, electrically erasable |