EP610JI-30 vs EP610ILC-10 Comparación
Comparación detallada lado a lado de EP610JI-30 por Altera y EP610ILC-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610JI-30 | EP610ILC-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,40 | $7,20 |
| Family | Altera Classic EPLD (EP610) | — |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | 16 |
| External Clocks | 2 | — |
| Tensión de alimentación | 5 V (single supply) | 5 V (single supply) |
| Process Technology | CMOS | — |
| Encapsulado | CQCC28 (windowed ceramic JLCC, J-bend) | PLCC-28 (plastic J-lead chip carrier) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| Temperatura de funcionamiento | -40C to +85C (industrial, per EP610 family suffix convention) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount (JLCC) | Surface Mount (PLCC socket or solder) |
| Estado RoHS | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |