EP610LC15 vs EP610LC-30 Comparación
Comparación detallada lado a lado de EP610LC15 por Rochester Electronics y EP610LC-30 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 Obsolete
Comparación de especificaciones
| Parámetro | EP610LC15 | EP610LC-30 |
|---|---|---|
| Marca | Rochester Electronics | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,45 | $16,40 |
| Device Family | Classic EPLD (EP610) | — |
| Number of Macrocells | 16 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (±10%) | 4.75 V to 5.25 V |
| Dedicated Inputs | 10 | — |
| I/O Pins | 16 | — |
| Total Logic Pins | 24 | — |
| Technology | UV-erasable EPROM, CMOS | CMOS EPROM (UV-erasable) |
| Encapsulado | PLCC-28 (J-Lead) | 24-pin CERDIP / PDIP |
| Temperatura de funcionamiento | 0 °C to +70 °C (LC suffix = commercial) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Programming Interface | Altera 4-pin serial (Classic algorithm) | — |
| Security Bit | Yes (programmable) | — |
| Estado RoHS | Compliant (Rochester re-creation) | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610) |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Tipo de montaje | — | Through-Hole |
| Tipo de salida | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |