EP610PC-20 vs EP610PC-15 Comparación
Comparación detallada lado a lado de EP610PC-20 por Altera y EP610PC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610PC-20 | EP610PC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $47,80 | $17,50 |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (single supply) |
| Número de pines | 24 | — |
| Encapsulado | PDIP-24 | PDIP-24 (plastic DIP, 24-pin) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| Estado RoHS | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Recuento de pines | — | 24 pins |
| Tipo de montaje | — | Through-Hole (DIP) |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |