EP610PC-30 vs EP610PC-15 Comparación
Comparación detallada lado a lado de EP610PC-30 por Altera y EP610PC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610PC-30 | EP610PC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,74 | $17,50 |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (single supply) |
| Process Technology | CMOS EPROM | — |
| Encapsulado | 24-pin PDIP (0.300 inch) | PDIP-24 (plastic DIP, 24-pin) |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| Estado RoHS | Not applicable (legacy non-compliant package per distributor listing) | [DATA_NEEDED: RoHS status] |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Recuento de pines | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |