EP9100C-30 vs EP910DC-30 Comparación
Comparación detallada lado a lado de EP9100C-30 por Altera y EP910DC-30 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP9100C-30 | EP910DC-30 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,95 | $15,60 |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Logic Density | 900 usable gates (approx.) | — |
| Macrocells | 48 | 24 |
| Flip-Flops | 24 | — |
| Dedicated Inputs | 24 | 36 |
| Propagation Delay (tPD) | 30 ns | 30 ns (max) |
| Maximum Toggle Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| I/O Standard | TTL-compatible | — |
| Technology | CMOS, UV-erasable (window) or OTP | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulado | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP | DIP-40 (through-hole, 600 mil) |
| Programming Method | JEDEC via Altera APU or compatible programmer | UV-Erasable / OTP |
| Tipo de montaje | Through-Hole (DIP) / Surface Mount (PLCC) | Through-Hole |
| Estado RoHS | [DATA_NEEDED: rohs_status] | — |
| Military Grade Variant | EP9100C-30/883 (MIL-STD-883 compliant) | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tensión de alimentación | — | 5 V |
| Process Technology | — | CMOS |