EP910DC-30 vs EP610DC-30 Comparación
Comparación detallada lado a lado de EP910DC-30 por Intel y EP610DC-30 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DC-30 | EP610DC-30 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,60 | $10,40 |
| Family | Classic EPLD (EP910 series) | EP610 (Classic Device Family) |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 16 |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 16 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Tensión de alimentación | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | — |
| Encapsulado | DIP-40 (through-hole, 600 mil) | 24-pin CERDIP (windowed) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Tipo de montaje | Through-Hole | Through-Hole |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |