EP910DM-40 vs EP910JC-35 Comparación
Comparación detallada lado a lado de EP910DM-40 por Altera y EP910JC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DM-40 | EP910JC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,00 | $9,95 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | — |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Encapsulado | 40-pin Ceramic DIP (Cerdip) with UV window | — |
| Tipo de montaje | Through-Hole (DIP) | Surface Mount (PLCC socket recommended) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to 70C (Commercial) |
| Tensión de alimentación | 5 V | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Logic Family | — | Classic EPLD (CMOS EPROM) |
| Inputs | — | 36 |
| I/O Pins | — | 24 |
| Propagation Delay (max) | — | 38 ns (tPD) |
| Frecuencia de reloj máxima | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | — | J BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Technology | — | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | — | COMMERCIAL |
| Equivalent Gates | — | Approx. 900 usable gates |