EP910ILC-12 vs EP910DC-15 Comparación
Comparación detallada lado a lado de EP910ILC-12 por Intel y EP910DC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910ILC-12 | EP910DC-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,40 | $10,75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Altera Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (typical) |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Encapsulado | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 24-pin ceramic DIP (DC) |
| Tipo de montaje | Surface Mount | Through-Hole |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial grade, 'I' suffix) | 0C to +70C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Número de pines | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |