EP910ILC-12 vs EP910ILC-50 Comparación
Comparación detallada lado a lado de EP910ILC-12 por Intel y EP910ILC-50 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910ILC-12 | EP910ILC-50 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,40 | $10,85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Altera Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | 900 (typical) |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (typical) |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Encapsulado | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | PLCC-44 (J-lead) |
| Tipo de montaje | Surface Mount | Surface Mount (socket-compatible) |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial grade, 'I' suffix) | 0C to +70C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Número de pines | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Macrocells | — | 24 |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| User I/O Pins | — | 24 |
| Dedicated Input Pins | — | 12 |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |