EP910ILC-25 vs EP910IPC-12 Comparación
Comparación detallada lado a lado de EP910ILC-25 por Intel y EP910IPC-12 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910ILC-25 | EP910IPC-12 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $14,20 |
| Family | EP910 Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPLD (UV-erasable or OTP) |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Encapsulado | 44-pin JLCC (windowed ceramic) | 40-pin PDIP |
| Tipo de montaje | Surface Mount | Through Hole |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Tensión de alimentación | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Estado RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Estado del ciclo de vida | Obsolete - last time buy was late 1990s | — |
| Usable Gates | — | 450 |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |