EP910ILC-50 vs EP910IPC-50 Comparación
Comparación detallada lado a lado de EP910ILC-50 por Intel y EP910IPC-50 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910ILC-50 | EP910IPC-50 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,85 | $13,85 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | 24 |
| Dedicated Input Pins | 12 | — |
| Encapsulado | PLCC-44 (J-lead) | 40-pin Ceramic DIP (IPC, windowed) |
| Tipo de montaje | Surface Mount (socket-compatible) | Through-Hole (DIP) |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM cell |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |