EP910IPC-12 vs EP910IDC-15 Comparación
Comparación detallada lado a lado de EP910IPC-12 por Altera y EP910IDC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IPC-12 | EP910IDC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $9,95 |
| Family | Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Dedicated Inputs | 10 | 10 |
| I/O Pins | 24 | 24 |
| Encapsulado | 40-pin PDIP | 40-pin CDIP (Ceramic DIP, through-hole) |
| Tipo de montaje | Through Hole | — |
| Technology | CMOS EPLD (UV-erasable or OTP) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | — |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | non_compliant (ceramic DIP contains lead) |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| Programming Technology | — | EPROM (UV-erasable) |