EP910IPC-25 vs EP910IPC-12 Comparación
Comparación detallada lado a lado de EP910IPC-25 por Intel y EP910IPC-12 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IPC-25 | EP910IPC-12 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $14,20 |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Temperatura de funcionamiento | 0C to +70C (commercial grade) | -40C to +85C (industrial) |
| Encapsulado | 40-pin PDIP (PDIP-40) | 40-pin PDIP |
| Tipo de montaje | Through-Hole | Through Hole |
| Programming Method | EPROM cell (OTP / UV erasable) | — |
| Development Tool | MAX+PLUS II | — |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| I/O Pins | — | 24 |
| Technology | — | CMOS EPLD (UV-erasable or OTP) |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |