EP910IPC-50 vs EP910ILC-25 Comparación
Comparación detallada lado a lado de EP910IPC-50 por Altera y EP910ILC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IPC-50 | EP910ILC-25 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,85 | $9,95 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | EP910 Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | 36 |
| Encapsulado | 40-pin Ceramic DIP (IPC, windowed) | 44-pin JLCC (windowed ceramic) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS EPROM cell | CMOS EPROM (UV-erasable) |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Tipo de montaje | Through-Hole (DIP) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: not stated in verified data] | non_compliant (ceramic windowed package) |
| Macrocells | — | 24 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Tensión de alimentación | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Estado del ciclo de vida | — | Obsolete - last time buy was late 1990s |