EP910IPC-50 vs EP910ILI-25 Comparación
Comparación detallada lado a lado de EP910IPC-50 por Altera y EP910ILI-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910IPC-50 | EP910ILI-25 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,85 | $7,25 |
| Product Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | — |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | — |
| Encapsulado | 40-pin Ceramic DIP (IPC, windowed) | PLCC-44 (windowed ceramic, J-lead) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Technology | CMOS EPROM cell | CMOS, EPROM |
| Programming Method | Off-board EPROM programmer + UV erase | UV-erasable (windowed), MAX+PLUS II programmer |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Tipo de montaje | Through-Hole (DIP) | — |
| Estado RoHS | [DATA_NEEDED: not stated in verified data] | Non-compliant (windowed ceramic package) |
| Series | — | EP910 (Classic EPLD) |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 (maximum) |
| Architecture | — | PAL-type with global interconnect bus |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Logic Test Circuitry | — | On-board JTAG-compatible test |