EP910LC-25 vs EP910LC-30Y Comparación
Comparación detallada lado a lado de EP910LC-25 por Intel y EP910LC-30Y por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-25 | EP910LC-30Y |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $2,20 | $25,40 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 16 | — |
| Encapsulado | 28-pin PLCC (LC suffix) | PLCC-44 |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket) |
| Technology | CMOS (EPROM-based) | — |
| Operating Voltage | [DATA_NEEDED: VCC range] | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial 0C to +70C |
| Programmable | Yes (EPROM, UV-erasable on windowed variants) | — |
| I/O Pins | [DATA_NEEDED: I/O count] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| Tensión de alimentación | — | 5 V (TTL-compatible) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |