EP910LC44-35 vs EP910LC-35T Comparación
Comparación detallada lado a lado de EP910LC44-35 por Intel y EP910LC-35T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC44-35 | EP910LC-35T |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $28,90 |
| Family | Classic EPLD (OT sub-family) | Classic EPLD (EP910) |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulado | 44-pin PLCC (J-leaded) | PLCC-44 (J-lead) |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket or solder) |
| Process Technology | CMOS | CMOS (EPROM-based) |
| Programmability | UV-erasable (windowed ceramic) | — |
| Logic Capacity | — | 450 usable gates |
| Maximum Operating Frequency | — | 28.6 MHz |
| User I/O Pins | — | 36 |
| Erasure Method | — | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| Nivel MSL | — | MSL 3 (168 hours) |
| Estado RoHS | — | [DATA_NEEDED: RoHS status not in verified data] |