EP910LI-30 vs EP910LI-50 Comparación
Comparación detallada lado a lado de EP910LI-30 por Rochester Electronics y EP910LI-50 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete
Comparación de especificaciones
| Parámetro | EP910LI-30 | EP910LI-50 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,50 | $65,00 |
| Family | Altera Classic EPLD EP910 | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | 50 ns |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V +/- 10% |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Encapsulado | 44-pin PQCC / PLCC-44 (J-lead) | — |
| Tipo de montaje | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 22 | [DATA_NEEDED: I/O pin count] |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | EPROM programmer (UV-erasable window) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Usable Gates | — | 450 |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Blocks | — | Classic AND/OR array architecture |
| Speed Grade Suffix | — | -50 (50 ns tPD) |