EP910LI-35Y vs EP910DC-30 Comparación
Comparación detallada lado a lado de EP910LI-35Y por Intel y EP910DC-30 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-35Y | EP910DC-30 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,75 | $15,60 |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: maximum toggle frequency in MHz] | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Option | L (low-power CMOS) | — |
| Temperature Grade | Industrial (-40 °C to +85 °C) | — |
| Encapsulado | PLCC-44 (J-lead) | DIP-40 (through-hole, 600 mil) |
| Tipo de montaje | Surface Mount | Through-Hole |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 36 | 36 |
| Technology | CMOS EPROM/UV-erasable | — |
| Estado RoHS | Compliant (Y suffix) | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tensión de alimentación | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |