EP910LI-50 vs EP910LI-12 Comparación
Comparación detallada lado a lado de EP910LI-50 por Altera y EP910LI-12 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LI-50 | EP910LI-12 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $65,00 | $15,95 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 50 ns | 12 ns |
| Package Type | CERDIP-40 (L) | — |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 4.75 V to 5.25 V (5 V typical) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 |
| Programming Method | EPROM programmer (UV-erasable window) | UV-erasable via windowed package |
| Estado RoHS | [DATA_NEEDED: RoHS status] | non_compliant (ceramic windowed package) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Frequency (fMAX) | — | 76.9 MHz |
| Inputs (with input registers) | — | 36 |
| Encapsulado | — | 28-PLCC (windowed ceramic, J-Lead) |
| Process Technology | — | 1.0-micron CMOS EPROM |
| Power Dissipation (typical) | — | 200 mW at 5 V |
| Logic Compatibility | — | TTL-compatible I/O |