EP910PC-20 vs EP910IPC-25 Comparación
Comparación detallada lado a lado de EP910PC-20 por Altera y EP910IPC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PC-20 | EP910IPC-25 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,40 | $10,40 |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Encapsulado | PDIP-24 (PC suffix) | 40-pin PDIP (PDIP-40) |
| Recuento de pines | 24 | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Programming Method | EPROM programmer, JEDEC fuse map | EPROM cell (OTP / UV erasable) |
| Tipo de montaje | Through-Hole (DIP) | Through-Hole |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |