EP910PI-15T vs EP910IPC-15 Comparación
Comparación detallada lado a lado de EP910PI-15T por Altera y EP910IPC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-15T | EP910IPC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $7,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD (EP910 series) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Tensión de alimentación | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 15 ns |
| Technology | CMOS EEPROM (electrically erasable) | — |
| Encapsulado | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (Plastic DIP, 40-pin) |
| Tipo de montaje | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial, IPC suffix) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| Estado RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Architecture | — | PAL-type, CMOS |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Recuento de pines | — | 40 |