EP910PI-15T vs EP910PI-25T Comparación
Comparación detallada lado a lado de EP910PI-15T por Altera y EP910PI-25T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-15T | EP910PI-25T |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $9,75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD Family |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Tensión de alimentación | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | CMOS, UV-erasable EPROM |
| Encapsulado | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | 40-pin PDIP (600-mil) |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial temp range] | [DATA_NEEDED: operating temperature range] |
| Programming | JEDEC-standard, serial/parallel programmer | UV-erasable |
| Estado RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | [DATA_NEEDED: RoHS compliance] |
| Equivalent Gates | — | 900 (SSI/MSI equivalent) |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Propagation Delay (tpd) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Static Power | — | <100 mW (typical CMOS) |