EP910PI-30T vs EP910PI-15T Comparación
Comparación detallada lado a lado de EP910PI-30T por Altera y EP910PI-15T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-30T | EP910PI-15T |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $10,95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | 12 |
| Propagation Delay (tPD) | 30 ns | 15 ns max (speed grade -15) |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EEPROM (electrically erasable) |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Tipo de montaje | Through-Hole | Through-Hole |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | JEDEC-standard, serial/parallel programmer |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Tensión de alimentación | — | 4.5 V to 5.5 V (5 V nominal) |
| Encapsulado | — | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |