EPC16UC88 vs EPC16UI88 Comparación
Comparación detallada lado a lado de EPC16UC88 por Altera y EPC16UI88 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC16UC88 | EPC16UI88 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | FPGA & CPLD |
| Estado del ciclo de vida | Unknown | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $5,21 |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| Tensión de alimentación | 3.3 V core and I/O | — |
| Encapsulado | 88-UBGA (11x8) | 88-ball UBGA (Ultra FineLine BGA), 11x8 mm |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| Tipo de montaje | Surface mount | Surface Mount |
| Package Dimensions | 11 mm x 8 mm | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature] | -40C to +85C (industrial) |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Memory Density | — | 16 Mb (2 MB) |
| Configuration Interface | — | Altera Passive Serial / Passive Parallel (Sync & Async) / JTAG |
| Core Supply Voltage | — | 3.3 V |
| Programming Interface | — | IEEE 1149.1 JTAG (in-system programmable) |
| Maximum Configuration Clock | — | 100 MHz |
| Cascading Support | — | Multi-device configuration chains |
| Supported FPGA Families | — | Altera Cyclone II/III/IV, Stratix II/III, APEX II |
| Standby Current | — | [DATA_NEEDED: standby current] |
| Active Configuration Current | — | [DATA_NEEDED: active configuration current] |
| Programming Cycles | — | [DATA_NEEDED: programming endurance cycles] |
| Configuration Time | — | [DATA_NEEDED: configuration time for typical 16 Mb bitstream] |