EPC16UC8B vs EPC16UC88 Comparación
Comparación detallada lado a lado de EPC16UC8B por Intel y EPC16UC88 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC16UC8B | EPC16UC88 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | NRND | Unknown |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,10 | $0,00 |
| Product Type | Enhanced Configuration Device | — |
| Manufacturer | Intel (formerly Altera) | — |
| Configuration Memory Density | 16 Mb | — |
| FPGA Family Supported | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX) | — |
| Configuration Modes | Passive Serial (PS), Passive Parallel Asynchronous (PPA), Passive Parallel Synchronous (PPS), Fast Passive Parallel (FPP) | — |
| Core Supply Voltage (VCC) | 3.3 V | — |
| I/O Supply Voltage (VIO) | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Configuration Pages | 16 pages x 1 Mb each | — |
| Encapsulado | 8-pin QFP (UC8B suffix) | 88-UBGA (11x8) |
| Tipo de montaje | Surface Mount | Surface mount |
| Temperatura de funcionamiento | [DATA_NEEDED: Operating temperature range] | [DATA_NEEDED: operating temperature] |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: Lead-free status] | — |
| Handshake Pins | nSTATUS, CONF_DONE, nCONFIG, OE | — |
| Family | EPC16 (Enhanced Configuration) | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tensión de alimentación | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |