EPC1LI20 vs EPC1L20 Comparación
Comparación detallada lado a lado de EPC1LI20 por Altera y EPC1L20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LI20 | EPC1L20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,50 | $3,75 |
| Tipo de memoria | OTP Configuration PROM (EPROM-based) | OTP Configuration PROM (Flash) |
| Tamaño de memoria | 1 Mb (1,048,576 bits) | 1 Mbit |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | — |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| Encapsulado | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (9x9 mm) |
| Recuento de pines | 20 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Through-Hole / Socket |
| Nivel MSL | 1 (per Partstack datasheet record) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | [DATA_NEEDED: RoHS compliance] |
| Configuration Clock (max) | — | 8 MHz |
| Flash Access Time | — | 90 ns (approx.) |
| Max Read Bandwidth | — | 160 Mbps (16-bit DQ bus) |
| Interfaz | — | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Tensión de alimentación | — | 3.3 V (typical) |
| Programmability | — | One-Time Programmable (OTP) |
| JTAG / ISP Support | — | Yes (IEEE 1149.1) |
| Compatible FPGA Series | — | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |