EPC2C20 vs EPC22LC20 Comparación
Comparación detallada lado a lado de EPC2C20 por Altera y EPC22LC20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2C20 | EPC22LC20 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $4,10 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Encapsulado | [DATA_NEEDED: package] | — |
| Recuento de pines | [DATA_NEEDED: pin count] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Función | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Tamaño de memoria | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (IEEE 1532 / Jam STAPL) |
| Supply Voltage - Low Range | — | 3.0 V to 3.6 V |
| Supply Voltage - High Range | — | 4.75 V to 5.25 V |
| Supported FPGA Families | — | ACEX 1K, APEX II, APEX 20K, FLEX 10K |
| Configuration Interface | — | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) |
| Programming Interface | — | JTAG (IEEE 1149.1 / IEEE 1532) |
| Encapsulado / Carcasa | — | 20-LCC (J-Lead, 9 x 9 mm) |
| Tipo de montaje | — | Surface Mount (PLCC socket compatible) |
| Packaging | — | Tube |
| Temperatura de funcionamiento | — | 0 C to +70 C (commercial) |
| Minimum DC Input Voltage | — | -0.3 V |
| Input Overshoot Tolerance | — | 7.0 V for <100 mA, <20 ns no-load |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns no-load |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status not in verified data] |