EPC2L120N vs EPC22LC20 Comparación
Comparación detallada lado a lado de EPC2L120N por Intel y EPC22LC20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2L120N | EPC22LC20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,85 | $4,10 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | — |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| Encapsulado | 84-pin PLCC (J-Lead) | — |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial temp range] | 0 C to +70 C (commercial) |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | ACEX 1K, APEX II, APEX 20K, FLEX 10K |
| Estado RoHS | unknown | — |
| Función | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Tamaño de memoria | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (IEEE 1532 / Jam STAPL) |
| Supply Voltage - Low Range | — | 3.0 V to 3.6 V |
| Supply Voltage - High Range | — | 4.75 V to 5.25 V |
| Configuration Interface | — | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) |
| Programming Interface | — | JTAG (IEEE 1149.1 / IEEE 1532) |
| Encapsulado / Carcasa | — | 20-LCC (J-Lead, 9 x 9 mm) |
| Tipo de montaje | — | Surface Mount (PLCC socket compatible) |
| Packaging | — | Tube |
| Minimum DC Input Voltage | — | -0.3 V |
| Input Overshoot Tolerance | — | 7.0 V for <100 mA, <20 ns no-load |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns no-load |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status not in verified data] |