EPC2L120N vs EPC2L20U Comparación
Comparación detallada lado a lado de EPC2L120N por Intel y EPC2L20U por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2L120N | EPC2L20U |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,85 | $10,55 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | — |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| Encapsulado | 84-pin PLCC (J-Lead) | 20-PLCC (PLCC-20) |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial temp range] | -40C to +85C (industrial) |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Tamaño de memoria | — | 1.6 Mbit |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Tipo de interfaz | — | Serial configuration (DCLK/DATA0) |
| Programmability | — | In-system programmable via IEEE 1532 / JTAG |
| Supported FPGAs | — | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K |
| Configuration Mode | — | Single + Cascade (multi-PROM daisy chain) |
| Compression Support | — | Yes (FPGA decompresses bitstream) |
| Tipo de montaje | — | Surface Mount / Socket |
| JTAG Support | — | Yes (IEEE Std 1149.1 boundary scan) |
| Recuento de pines | — | 20 |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |