EPC2L120N vs EPC2L20U-HAF480119C Comparación
Comparación detallada lado a lado de EPC2L120N por Intel y EPC2L20U-HAF480119C por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Última compraComparación de especificaciones
| Parámetro | EPC2L120N | EPC2L20U-HAF480119C |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,85 | $10,75 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | — |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| Encapsulado | 84-pin PLCC (J-Lead) | PLCC-20 |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial temp range] | — |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Tipo de memoria | — | Configuration PROM (non-volatile) |
| Tamaño de memoria | — | 1.6 Mb |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Cascade Support | — | Yes (multi-PROM chains for larger FPGAs) |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Tipo de montaje | — | Surface Mount / Socketed |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |