EPC2LI20PULLS vs EPC2LI20N Comparación
Comparación detallada lado a lado de EPC2LI20PULLS por Intel y EPC2LI20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LI20PULLS | EPC2LI20N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $5,10 |
| Tipo de memoria | Serial Configuration Flash PROM | Non-volatile configuration PROM (Flash) |
| Tamaño de memoria | 1.6 Mbit | 1.6 Mbit |
| Configuration Interface | Serial (Altera FPP / PS modes) | — |
| Frecuencia de reloj máxima | 10 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Tolerance | 5 V tolerant configuration pins | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Compression Support | Yes (real-time decompression in target FPGA) | — |
| Multi-Device Cascade | Yes (daisy-chain supported) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado | 20-pin PLCC (J-Lead, 9x9 mm) | — |
| Tipo de montaje | Surface Mount / Socket | Surface Mount |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur | — |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Encapsulado / Carcasa | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |