EPC4QI100N vs EPC4Q100N Comparación
Comparación detallada lado a lado de EPC4QI100N por Altera y EPC4Q100N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPC4QI100N - 4Mb In-System Programmable FPGA Config PROM | Altera (Intel)
EPC4QI100N ✓ Activo
Comparación de especificaciones
| Parámetro | EPC4QI100N | EPC4Q100N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | FPGA & CPLD |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $21,05 |
| Tipo de memoria | In-System Programmable Configuration PROM (NOR flash) | Flash (NOR, Enhanced Configuration Device) |
| Tamaño de memoria | 4 Mbit (4,194,304 bits) | 4 Mbit (512 Kbyte) |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Interfaz | Altera serial (x1) configuration + JTAG | — |
| Configuration Clock DCLK | [DATA_NEEDED: DCLK maximum frequency] | — |
| Active Supply Current (ICC active) | [DATA_NEEDED: ICC active typical value] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby typical value] | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Storage Temperature | -65C to +150C | — |
| Encapsulado | 100-pin PQFP (PowerPQFP, 20x14 mm) | 100-pin PQFP |
| Package Code | QI100 (PQFP-100, industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: per JEDEC J-STD-020] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | — |
| JTAG Standard | IEEE 1149.1 boundary-scan / ISP | — |
| Cascading | Supported (multi-device daisy chain) | — |
| Target FPGAs | Altera Cyclone, Cyclone II, Stratix series | — |
| Configuration Interface | — | Serial (FLEX) / Parallel / JTAG ISP |
| Tensión de alimentación | — | 3.3 V |
| Program/Erase Cycles | — | [DATA_NEEDED: minimum endurance in cycles] |
| JTAG Support | — | IEEE 1149.1 compliant |
| In-System Programmable | — | Yes |
| Target FPGA Families | — | Cyclone, Stratix, APEX, Mercury, ACEX |
| Data Width (parallel mode) | — | 8-bit |
| Lead-Free / RoHS | — | [DATA_NEEDED: per lot] |
| Status | — | Not Recommended for New Designs (NRND) |
| Configuration Schemes | — | Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS) |