EPF10K100BFC256-1 vs EPF10K100EFC256-2 Comparación
Comparación detallada lado a lado de EPF10K100BFC256-1 por Altera y EPF10K100EFC256-2 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPF10K100BFC256-1 - FLEX-10K 100K-Gate FPGA | Intel/Altera | 256-BGA
EPF10K100BFC256-1 ObsoleteIntel
EPF10K100EFC256-2 - FLEX 10KE FPGA, 100K Gates, 256-BGA | Intel / Altera
EPF10K100EFC256-2 NrndComparación de especificaciones
| Parámetro | EPF10K100BFC256-1 | EPF10K100EFC256-2 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $105,00 | $165,00 |
| Series | FLEX-10K® | FLEX 10KE |
| Family | FLEX-10K (100K gates) | — |
| Total RAM Bits | 6144 | [DATA_NEEDED: total EAB RAM bits] |
| Number of Logic Elements | 576 | — |
| Number of Gates | 100,000 typical system gates | 100,000 equivalent |
| Number of I/O | 244 (approx.) | — |
| Tensión de alimentación | 4.75 V to 5.25 V | — |
| Temperatura de funcionamiento | 0°C to +70°C (commercial) | 0 °C to +70 °C (Commercial) |
| Speed Grade | -1 (fastest) | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Encapsulado | 256-FBGA (17 mm x 17 mm) | 256-FBGA (FineLine BGA, 17 x 17 mm) |
| Supplier Device Package | 256-FBGA | — |
| Form of Terminal | Ball | — |
| Number of Terminals | 256 | — |
| JTAG Support | IEEE Std 1149.1 boundary-scan | — |
| Process Technology | 0.42 µm SRAM-based CMOS | 0.22 µm CMOS SRAM |
| Configuration Mode | In-system programmable (ByteBlaster/BitBlaster) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements / Cells | — | 4,992 (49,152 user logic elements) |
| Number of LABs | — | 624 |
| User I/Os | — | 191 |
| Core Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Logic Family | — | CMOS (SRAM-based) |
| Propagation Delay (per LUT) | — | ~0.6 ns (speed grade -2) |
| Configuration Method | — | PS, JTAG, in-system programmable |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Embedded Array Blocks | — | Yes (EAB for RAM/ROM/DSP) |