EPF10K100EQC240-1X vs EPF10K100EQC240-1 Comparación
Comparación detallada lado a lado de EPF10K100EQC240-1X por Intel y EPF10K100EQC240-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPF10K100EQC240-1X | EPF10K100EQC240-1 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $65,00 | $18,50 |
| Series | FLEX 10KE | FLEX-10KE |
| Family | FLEX 10KE Field Programmable Gate Array | FLEX 10KE |
| System Gates | 100,000 | — |
| Logic Cells | 4,992 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Total RAM Bits | 49,152 | 49152 |
| User I/Os | 189 | — |
| Core Voltage | 2.375 V to 2.625 V (typ. 2.5 V) | — |
| Maximum Internal Clock Frequency | 333.33 MHz | — |
| Process Technology | 0.22 um CMOS | CMOS (0.42 µm) |
| Encapsulado | 240-BFQFP / PQFP, 32 x 32 mm | 240-BFQFP (PQFP240, 32 x 32 mm) |
| Tipo de montaje | Surface Mount, gull-wing leads | Surface Mount |
| Packaging | Tray | — |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Peak Reflow Temperature (Max) | 30 s [DATA_NEEDED: peak temperature deg C] | — |
| JTAG Compliance | IEEE Std. 1149.1-1990 BST | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (3.3 V and 5.0 V operation, -1 speed grade) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs] |
| Logic Elements / Cells | — | 4992 |
| Number of LABs / CLBs | — | 624 |
| Typical Gate Count | — | 100000 |
| Number of User I/Os | — | 189 |
| Supply Voltage (Core) | — | 2.375 V to 2.625 V |
| I/O Voltage | — | 3.3 V (MultiVolt: 1.8 V / 2.5 V / 3.3 V) |
| Propagation Delay | — | 0.4 ns to 0.6 ns |
| Temperatura de funcionamiento | — | 0 °C to 70 °C (Commercial) |
| Estilo de montaje | — | SMD / SMT |
| Configuration Method | — | SRAM (serial / JTAG) |
| Embedded Memory | — | EABs (12 blocks × 2048 bits) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Status | — | Obsolete (EOL) |