EPF10K200SFC672-1 vs EPF10K200SFC672-1X Comparación
Comparación detallada lado a lado de EPF10K200SFC672-1 por Altera y EPF10K200SFC672-1X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPF10K200SFC672-1 | EPF10K200SFC672-1X |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $138,75 | $135,00 |
| Series | FLEX 10KE | FLEX-10KS |
| Family | FLEX 10KE (FLEX-10KS) | FLEX 10K (legacy) |
| Logic Elements / Cells | 9984 | — |
| Total RAM Bits | 98304 | — |
| Number of LABs/CLBs | 1248 | — |
| Number of User I/Os | 470 | — |
| Number of Gates | 200K system gates | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt) | — |
| Maximum Operating Frequency | 250 MHz | — |
| Propagation Delay | 0.4 ns | 0.4 ns |
| Process Technology | 0.22 µm CMOS, SRAM-based | — |
| Package Type | 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (Commercial) | 0 °C to 70 °C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) + serial/parallel passive configuration | — |
| Embedded Array Blocks (EABs) | 12 | 24 |
| Speed Grade | -1 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Architecture | — | Reconfigurable CMOS SRAM |
| Typical System Gates | — | 200,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gate count] |
| Logic Elements (LEs) | — | 9,984 |
| Logic Array Blocks (LABs) | — | 1,248 |
| Embedded RAM Bits | — | 98,304 |
| User I/O Pins | — | 470 |
| Core Supply Voltage | — | 2.375 V to 2.625 V (2.5 V nominal) |
| JTAG Support | — | IEEE Std. 1149.1 (adds up to 31,250 gates) |
| Encapsulado | — | 672-ball FineLine BGA, 27 × 27 mm, 1.0 mm pitch |
| Logic Family | — | CMOS |
| Configuration Method | — | SRAM (volatile, reconfigurable at every power-up) |
| Design Tool | — | Quartus (legacy FLEX 10K support) |