EPF10K50VQC240-2 vs EPF10K50EQC240-2N Comparación
Comparación detallada lado a lado de EPF10K50VQC240-2 por Altera y EPF10K50EQC240-2N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPF10K50EQC240-2N - FLEX 10KE FPGA 50K Gates 240-PQFP | Intel / Altera
EPF10K50EQC240-2N ObsoleteComparación de especificaciones
| Parámetro | EPF10K50VQC240-2 | EPF10K50EQC240-2N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,75 | $87,20 |
| Family | FLEX 10K | FLEX 10KE |
| Series | FLEX-10K | — |
| Typical Gate Count | 50,000 gates | — |
| Logic Elements (LABs) | 360 | — |
| Logic Cells | 2,880 | — |
| Embedded Array Memory | 20,480 bits | — |
| User I/O Pins | 189 | — |
| Encapsulado | 240-BFQFP (240-PQFP / FQFP / QFP-240) | 240-pin PQFP / BFQFP |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Package Code | FQFP | — |
| Package Shape | Square | — |
| Process Technology | 0.42 micrometer CMOS, 4-layer metal | 0.22 µm CMOS |
| Core Supply Voltage | 3.3 V | — |
| I/O Supply Voltage (MultiVolt) | 5.0 V / 3.3 V / 2.5 V | — |
| Maximum Internal Frequency | 125 MHz | — |
| Propagation Delay (typical) | 0.6 ns | — |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | 0 °C to +70 °C (commercial) |
| Temperature Grade | Commercial | — |
| Configuration Scheme | SRAM-based, serial / parallel via EPC1/EPC2 | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy Altera FLEX 10K family typically non-RoHS Pb-bearing BFQFP; verify on distributor listing] | [DATA_NEEDED: RoHS status - older FLEX 10KE part, likely non-compliant] |
| Logic Elements (LEs) | — | 2,880 |
| Logic Array Blocks (LABs) | — | 360 |
| Typical Gates | — | 50,000 |
| Embedded SRAM | — | 40,960 bits (5,120 bytes) |
| Embedded Array Blocks (EABs) | — | 4 |
| Maximum User I/Os | — | 189 |
| Internal Supply Voltage (VCCINT) | — | 2.5 V |
| Internal Performance | — | 200 MHz |
| Propagation Delay | — | 0.6 ns |
| Configuration Method | — | JTAG / external EPC PROM / intelligent controller |
| I/O Standards Supported | — | PCI, LVTTL, LVCMOS (5.0 V / 3.3 V / 2.5 V) |
| PCI Compliance | — | PCI-SIG compliant |