EPF6010ATC100-2 vs EPF6016AFC100-3 Comparación
Comparación detallada lado a lado de EPF6010ATC100-2 por Altera y EPF6016AFC100-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPF6010ATC100-2 - FLEX 6000 FPGA, 880 Gates, 71 I/O | Intel (Altera)
EPF6010ATC100-2 Obsolete
Comparación de especificaciones
| Parámetro | EPF6010ATC100-2 | EPF6016AFC100-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $18,23 |
| Series | FLEX 6000 | — |
| Family | SRAM-based FPGA | FLEX 6000 |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements / Gates | 880 gates (typical) | — |
| Logic Array Blocks (LABs) | 88 | — |
| User I/O Pins | 71 | — |
| Number of Logic Cells | 880 (per FLEX 6000 family datasheet) | — |
| Encapsulado | 100-pin TQFP (14x14 mm) | 100-pin FineLine BGA (FBGA) |
| Speed Grade | -2 | — |
| Temperatura de funcionamiento | 0C to 70C (commercial) | 0 C to 85 C (Commercial) |
| Core Supply Voltage | 3.0 V to 3.6 V (typical 3.3 V) | — |
| I/O Supply Voltage | 3.3 V (5 V tolerant inputs per FLEX 6000 family) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Process Node | [DATA_NEEDED: CMOS process node] | — |
| Total RAM Bits | [DATA_NEEDED: embedded RAM] | — |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Gates | — | 16,000 gates |
| Logic Cells | — | 1,320 cells |
| Maximum Internal Frequency | — | 142.86 MHz |
| Process Technology | — | 0.42 um CMOS |
| User I/O | — | 81 |
| Tensión de alimentación | — | 3.3 V |
| Architecture | — | SRAM-based, 4-input LUT |
| Configuration Method | — | SRAM (in-system programmable) |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |