EPF8820ARC208-2N vs EPF8820ARC208-3 Comparación
Comparación detallada lado a lado de EPF8820ARC208-2N por Altera y EPF8820ARC208-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoleteComparación de especificaciones
| Parámetro | EPF8820ARC208-2N | EPF8820ARC208-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $20,55 | $62,00 |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Usable Gates | 8,000 | 8,000 |
| Logic Elements (Cells) | 672 | — |
| Maximum Operating Frequency | 125 MHz | 125 MHz |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS |
| Supply Voltage (VCCINT) | 5 V | — |
| Output Supply Voltage (VCCIO) | 3.3 V or 5.0 V (bank-selectable) | — |
| User I/O Pins | 152 | — |
| Maximum Outputs | 148 | — |
| Dedicated Inputs | 4 | — |
| Encapsulado | 208-pin RQFP / BFQFP with Exposed Pad | — |
| Configuration Method | Serial (EPC1/EPC1213/EPC1064/EPC1441) or Parallel EPROM | — |
| In-Circuit Reconfigurability | Yes | — |
| JTAG Boundary-Scan | Yes | — |
| Operating Temperature (Industrial -N suffix) | -40 °C to +85 °C | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Memory | — | SRAM (volatile) |
| Encapsulado / Carcasa | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |